1. Field of the Invention
The present invention relates to a capacitor and a method of fabricating the same, and more particularly, to a capacitor in a shallow trench isolation (hereinafter referred to as “STI”) region, and a method of fabricating the same. The present invention may increase the capacitance per unit area of the capacitor, and/or may reduce an interlayer dielectric layers thickness.
2. Background of the Related Art
Referring to FIG. 1a, a field oxide layer 11 and a gate oxide layer 12 are formed for the insulation between devices on a semiconductor substrate 10. A first polysilicon layer 13, which may be used as a gate electrode and a lower electrode of a capacitor, is deposited on the gate oxide layer 12 and doped.
Referring to FIG. 1b, using a selective dry etch process and a mask, a gate electrode 14 is formed on the gate oxide layer 12 and a lower electrode 15 of a poly-insulator-poly (hereinafter referred to as “PIP”) capacitor is formed on the field oxide layer 11.
Referring to FIG. 1c, an insulation layer 16 is blanket deposited on the substrate, including where the gate electrode 14 and the polysilicon lower electrode 15 are formed. The insulation layer 16 may be formed by depositing an oxide layer (e.g., SiO2) using a LPCVD (low pressure chemical vapor deposition) process.
Referring to FIG. 1d, a second polysilicon layer 17 for an upper electrode of a PIP capacitor is deposited on the insulation layer 16.
Referring to FIG. 1e, the upper electrode 18 of a PIP capacitor is formed using a selective dry etch process and a mask. During a second stage of the etch process, the insulation layer 16 (except under the upper electrode 18) is removed.
Referring to FIG. 1f, a source and a drain of a MOS transistor are formed using an ion implantation process, and an insulation layer 20 (e.g., comprising TEOS (tetra-ethyl-ortho-silicate) layer and/or a BPSG (borophosphosilicate glass) is formed through a CVD (chemical vapor deposition) process. Contact holes are formed to connect overlying metal interconnects with the source, the drain, and the lower electrode of the PIP capacitor. Contact plugs 19 are then formed by filling metals into the contact holes.
Korean Patent Publication No. 2003-0072111 describes a method of fabricating a PIP capacitor on a field oxide layer. More particularly, the method reduces resistance-capacitance (hereinafter referred to as “RC”) delay and gate sheet resistance by implanting POCl3 ions or P ions into the polysilicon layer of a gate electrode and a capacitor. Korean Patent Publication No. 2002-0030420 describes a method which enhances the linear characteristic of a capacitor by forming the lower electrode of a capacitor with a silicon layer and a silicide layer, and forming the upper electrode of the capacitor with a metal. U.S. Pat. No. 6,492,224 describes a method of fabricating the lower electrode of a capacitor by etching the insulation layer of an STI region, then filling the etched trench with polysilicon.
However, in the prior method(s) of fabricating both a PIP capacitor and a MOS transistor, the PIP capacitor is formed on the field oxide layer or on the STI layer, and both a gate electrode and at least one polysilicon layer of a capacitor are formed using the same polysilicon layer. Consequently, when the lower electrode of the capacitor and the gate are formed from the same polysilicon layer, a height profile difference between the gate electrode and the capacitor arises, plasma damage may be caused, and the interlayer dielectric may thicken, making contact plug formation more difficult.